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1、半帶濾波器的VHDL源程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY HALFBAND IS
PORT(SYSCLK:IN STD_LOGIC;
CLKA:IN STD_LOGIC;
CLKB:IN STD_LOGIC;
IFS:IN STD_LOGIC; --2.56M
DATAIN:IN STD_LOGIC_VECTOR(11 DOWNTO 0 );
DATAOUT:BUFFER STD_LOGIC_VECTOR(11 DOWNTO 0 ));
END HALFBAND;
ARCHITECTURE BEHAVIORAL OF HALFBAND IS
SIGNAL DATAIN_NEXT1:STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL DATAIN_NEXT2:STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL DATAOUT_TMP:STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL DCM_INP_COUNT:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL DCM_INP_FLAG:STD_LOGIC;
SIGNAL DATAINE :STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL CLK_A_HALF:STD_LOGIC;
COMPONENT HB_CORE IS
PORT(SYSCLK:IN STD_LOGIC;
CLKA:IN STD_LOGIC;
CLKB:IN STD_LOGIC;
IFS:IN STD_LOGIC; --2.56M
DATAIN :IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DATAOUT:BUFFER STD_LOGIC_VECTOR(11 DOWNTO 0));
END COMPONENT HB_CORE;
BEGIN
UL:HB_CORE
PORT MAP(SYSCLK=>SYSCLK,CLKA=>CLKA,CLKB=>CLKB,IFS=>IFS,
DATAIN=>DATAIN,DATAOUT=>DATAIN_NEXT1);
U2:HB_CORE
PORT MAP(SYSCLK=>SYSCLK,CLKA=>CLK_A_HALF,CLKB=>CLKB,IFS=>IFS,
DATAIN=>DATAIN_NEXT2,DATAOUT=>DATAOUT_TMP);
DATAINE<=DATAIN&"0000";
PROCESS(CLKA)
BEGIN
IF CLKA ='1' AND CLKA'EVENT THEN
DCM_INP_FLAG<=NOT DCM_INP_FLAG;
DCM_INP_COUNT<=DCM_INP_COUNT+1;
CLK_A_HALF<=NOT CLK_A_HALF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF CLKA='1' AND CLKA'EVENT THEN
IF DCM_INP_FLAG='1'THEN
DATAIN_NEXT2<=DATAIN_NEXT1;
END IF;
IF DCM_INP_COUNT="11" THEN
DATAOUT_TMP<=DATAOUT;
END IF;
END IF;
END PROCESS;
END BEHAVIORAL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HB_CORE IS
PORT(
SYSCLK:IN STD_LOGIC;
CLKA:IN STD_LOGIC;
CLKB:IN STD_LOGIC;
IFS:IN STD_LOGIC; --2.56M
DATAIN : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DATAOUT:BUFFER STD_LOGIC_VECTOR(11 DOWNTO 0));
END HB_CORE;
--15 ORDERS HALFBAND FILTER
---COE ARE:
---0,33,0,-114,0,479,782,478, 0，-114,0, 33，0,-6
---IN FACT IT HAVE 9 TAPS
---WE USE MULTI-PHASE STRUCTURE
---WE USE DISTRIBUTION ARITH
ARCHITECTURE BEHAVIORAL2 OF HALFBAND IS
SIGNAL TAP0: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL TAP1: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL TAP2: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL TAP3: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL TAP4: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL TAP5: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL TAP6: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL DATAIN_D: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL TAPA0: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL TAPA1: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL TAPA2: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL TAPA2E: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL DATAINE: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL TAP0E: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL TAP1E: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL TAP2E: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL TAP3E: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL TAP4E: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL TAP5E: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL TAP6E: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL SUBSUM1: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL SUBSUM2: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL SUBSUM3: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL SUBSUM4: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL A:STD_LOGIC;
SIGNAL SHIFTER1: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL SHIFTER2: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL SHIFTER3: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL SHIFTER4: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL SHIFTER5: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL SHIFTER6: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL T1: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL T2: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL T3: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL T4: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL T5: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL T5_D: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL T5_2D: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL SUM1: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL SUM2: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL SUM3: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL SUMDATA: STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL ACCDATAA: STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL SUMDATAE: STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL T5_2DE: STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL COUNT: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DATAODD: STD_LOGIC_VECTOR(11 DOWNTO 0);
BEGIN
---THE FILTER IS DIVIDED INTO TWO PARTS
-------HERE WE COMPUTE ODD PHASE FILTERS
-------8 TAPS DELAY LINE
-------THEN SUM THE SYM TAPS
-------THE SUBSUMDATA GO INTO SHIFTERS TO
-------DISTRIBUTION ARITH MODULE
DATAINE(12)<=DATAIN(11);
DATAINE(11 DOWNTO 0)<=DATAIN;
TAP0E(12)<=TAP0(11);
TAP0E(11 DOWNTO 0)<=TAP0;
TAP1E(12)<=TAP1(11);
TAP1E (11 DOWNTO 0 )<=TAP1 ;
TAPA2E(12)<=TAPA2(11);
TAPA2E(11 DOWNTO 0)<=TAPA2;
TAP2E(12)<=TAP2(11);
TAP2E(11 DOWNTO 0)<=TAP2;
TAP3E(12)<=TAP3(11);
TAP3E(11 DOWNTO 0)<=TAP3;
TAP4E(12)<=TAP4(11);
TAP4E(11 DOWNTO 0)<=TAP4;
TAP5E(12)<=TAP5(11);
TAP5E(11 DOWNTO 0)<=TAP5;
TAP6E(12)<=TAP6(11);
TAP6E(11 DOWNTO 0)<=TAP6;
TAPA2E(12)<=TAPA2(11);
TAPA2E(11 DOWNTO 0)<=TAPA2;
PROCESS(SYSCLK)
BEGIN
IF SYSCLK ='1' AND SYSCLK'EVENT THEN
IF CLKA='1' THEN
COUNT<="00000000";
ELSIF IFS='1'THEN
COUNT<=COUNT+1;
END IF;
IF CLKB='1' THEN
DATAIN_D<=DATAIN;
END IF;
IF CLKA='1' THEN
TAP0<=DATAIN;
TAP1<=TAP0;
TAP2<=TAP1;
TAP3<=TAP2;
TAP4<=TAP3;
TAP5<=TAP4;
TAP6<=TAP5;
TAPA0<=DATAIN_D;
TAPA1<=TAPA0;
TAPA2<=TAPA1;
END IF;
IF IFS='1'AND COUNT="00000001" THEN
SUBSUM1<= DATAINE+TAP6E;
SUBSUM2<=TAP0E+TAP5E;
SUBSUM3<=TAP1E+TAP4E;
SUBSUM4<=TAP2E+TAP3E;
END IF;
END IF;
END PROCESS;
PROCESS(SYSCLK)
BEGIN
IF SYSCLK ='1'AND SYSCLK'EVENT THEN
IF IFS ='1' AND COUNT= "00000100" THEN
SHIFTER1<= SUBSUM1;
SHIFTER2<= SUBSUM2;
SHIFTER3<= SUBSUM3;
SHIFTER4<= SUBSUM4;
SHIFTER5<= TAPA2E;
ELSIF IFS='1' THEN
SHIFTER1<=SHIFTER1(11 DOWNTO 0)&'0';
SHIFTER2<=SHIFTER2(11 DOWNTO 0 )&'0';
SHIFTER3<=SHIFTER3(11 DOWNTO 0 )&'0';
SHIFTER4<=SHIFTER4(11 DOWNTO 0)&'0';
SHIFTER5<=SHIFTER5(11 DOWNTO 0)&'0';
END IF;
END IF;
END PROCESS;
-------DISTRIBUTION ARITH MODULE
-------FIRST EVERY BIT OF EVERY SUBSUM GO INTO LOOKTABLES
-------TO GET THEN PRODUCT
PROCESS(SYSCLK)
BEGIN
IF SYSCLK ='1'AND SYSCLK'EVENT THEN
IF IFS = '1' THEN
IF SHIFTER1(12)='1' THEN
T1<= "111111111010"; --------6
--TL="111111110110"; ------10
ELSE
T1<="000000000000";
END IF;
IF SHIFTER2(12)='1' THEN
T2<="000000100001";
--T2<="000000110101";
ELSE
T2<="000000000000";
END IF;
IF SHIFTER3(12)='1' THEN
T3<="111110001110";
--T3<="111101000111";
ELSE
T3<="000000000000";
END IF;
IF SHIFTER4(12)='1' THEN
T4<="000111011110";
--T4<="001100000110";
ELSE
T4<="000000000000";
END IF;
IF SHIFTER5(12)= '1' THEN
T5<="001100001110"; --782 126ITS
--T5<-"010011110011"; 一一1267 12BITS
ELSE
T5<="000000000000";
END IF;
END IF;
END IF;
END PROCESS;
----THENW EG ET4 P RODUCT瑆E SHOULD SUM THEM
SUMDATAE(23)<=SUMDATA(11);
SUMDATAE(22)<=SUMDATA(11);
SUMDATAE(21)<=SUMDATA(11);
SUMDATAE(20)<=SUMDATA(11);
SUMDATAE(19)<=SUMDATA(11);
SUMDATAE(18)<=SUMDATA(11);
SUMDATAE(17)<=SUMDATA(11);
SUMDATAE(16)<=SUMDATA(11);
SUMDATAE(15)<=SUMDATA(11);
SUMDATAE(14)<=SUMDATA(11);
SUMDATAE(13)<=SUMDATA(11);
SUMDATAE(12)<=SUMDATA(11);
SUMDATAE(11 DOWNTO 0)<=SUMDATA;
PROCESS(SYSCLK,SUMDATA)
BEGIN
IF (SYSCLK='1'AND SYSCLK'EVENT)THEN
IF (IFS='1')THEN
SUM1<= T1+T2;
SUM2<= T4+T3;
T5_D<= T5;
SUM3<=SUM2+SUM1;
T5_2D<=T5_D;
SUMDATA<=SUM3+T5_2D;
END IF;
IF COUNT="00000010" THEN
ACCDATAA<="000000000000000000000000";
ELSIF IFS='1'AND COUNT="00001001" THEN
ACCDATAA<=ACCDATAA(22 DOWNTO 0 )&'0'-SUMDATAE;
ELSIF IFS='1'THEN
ACCDATAA<=ACCDATAA(22DOWNTO 0 )&'0'+SUMDATAE;
END IF;
IF IFS ='1' AND COUNT= "00010110" THEN
DATAODD<=ACCDATAA(21 DOWNTO 10);
END IF;
IF CLKA ='1' THEN
DATAOUT<=DATAODD;
END IF;
END IF;
END PROCESS;
END BEHAVIORAL2;
2、FIR濾波器的VHDL代碼
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.SIGNED_ARITH.ALL;
USE WORK.COEFFS.ALL;
ENTITY FIR IS
PORT( CLK,RESET: IN STD_LOGIC;
SAMPLE: IN SIGNED ( 7 DOWNTO 0);
RESULT: OUT SIGNED ( 16 DOWNTO 0));
END FIR;
ARCHITECTURE BEH OF FIR IS
BEGIN
FIR_MAIN :PROCESS
TYPE SHIFT_ARR IS ARRAY (16 DOWNTO 0) OF SIGNED (7 DOWNTO 0);
VARIABLE TMP,OLD:SIGNED( 7 DOWNTO 0);
VARIABLE PRO:SIGNED (16 DOWNTO 0);
VARIABLE ACC:SIGNED (16 DOWNTO 0);
VARIABLE SHIFT:SHIFT_ARR;
BEGIN
RESET_LOOP:LOOP
FOR I IN 0 TO 15 LOOP --ZERO OUT THE SHIFT REGISTER
SHIFT(I):=(OTHERS=>'0');
END LOOP;
RESULT<=(OTHERS=>'0');
WAIT UNTIL CLK'EVENT AND CLK='1';
IF RESET='1' THEN EXIT RESET_LOOP;
END IF;
MAIN:LOOP
TMP:=SAMPLE;
PRO:=TMP*COEFS(0);
ACC:=PRO;
FOR 1 IN 15 DOWNTO 0 LOOP
OLD:=SHIFT(1);
PRO:=OLD*COEFS(1+1);
ACC:=ACC+PRO;
SHIFT(1+1):=SHIFT(1);
END LOOP;
SHIFT(0):=TMP;
RESULT<=ACC;
WAIT UNTIL CLK'EVENT AND CLK='1';
IF RESET='1' THEN EXIT RESET_LOOP;
END IF;
END LOOP MAIN;
END LOOP RESET_LOOP;
END PROCESS;
END BEH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
-USE WORK.SIGNED_ARITH.ALL;
USE WORK.COEFFS.ALL;
ENTITY FIR IS
PORT( CLK,RESET: IN STD_LOGIC;
SAMPLE: IN SIGNED ( 7 DOWNTO 0);
RESULT: OUT SIGNED ( 16 DOWNTO 0));
END FIR;
ARCHITECTURE BEH OF FIR IS
BEGIN
FIR_MAIN :PROCESS
TYPE SHIFT_ARR IS ARRAY (16 DOWNTO 0) OF SIGNED (7 DOWNTO 0);
VARIABLE TMP,OLD:SIGNED( 7 DOWNTO 0);
VARIABLE PRO:SIGNED (16 DOWNTO 0);
VARIABLE ACC:SIGNED (16 DOWNTO 0);
VARIABLE SHIFT:SHIFT_ARR;
BEGIN
RESET_LOOP:LOOP
FOR 1 IN 0 TO 15 LOOP --ZERO OUT THE SHIFT REGISTER
SHIFT(I):=(OTHERS=>'0');
END LOOP;
RESULT<=(OTHERS=>'0');
WAIT UNTIL CLK'EVENT AND CLK='1';
IF RESET='1' THEN EXIT RESET_LOOP;
END IF;
MAIN:LOOP
TMP:=SAMPLE;
PRO:=TMP*COEFS(0);
ACC:=PRO;
FOR 1 IN 15 DOWNTO 0 LOOP
OLD:=SHIFT(I);
PRO:=OLD*COEFS(1+1);
ACC:=ACC+PRO;
SHIFT(1+1):=SHIFT(1);
END LOOP;
SHIFT(0):=TMP;
RESULT<=ACC;
WAIT UNTIL CLK'EVENT AND CLK='1';
IF RESET='1' THEN EXIT RESET_LOOP;
END IF;
END LOOP MAIN;
END LOOP RESET_LOOP;
END PROCESS;
END BEH;
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